发明名称 Verfahren zum Verpacken von integrierten Schaltungen auf Waferniveau, zusammengesetzter Wafer und Packung auf Waferniveau
摘要 A wafer-level packaged IC is made by attaching a cap wafer to the top of an IC wafer before cutting the IC wafer, i.e. before singulating the plurality of die on the IC wafer. The cap wafer is mechanically attached and electrically connected to the IC wafer, then the die are singulated. Electrically conductive paths extend through the cap wafer, between wafer contact pads on the top surface of the cap and electrical contact points on the IC wafer. Optionally, the cap wafer contains one or more die. The IC wafer can be fabricated according to a different technology than the cap wafer, thereby forming a hybrid wafer-level package. Optionally, additional "upper-level" cap wafers (with or without die) can be stacked to form a "multi-story" IC.
申请公布号 DE102006012645(B4) 申请公布日期 2010.06.02
申请号 DE20061012645 申请日期 2006.03.20
申请人 MEMSIC INC. 发明人 ZHAO, YANG
分类号 H01L21/50;B81C3/00;H01L23/04;H01L23/14;H01L25/065 主分类号 H01L21/50
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