发明名称
摘要 A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps. Preferably, the conductor plate is composed of a multilayer structure of two or more layers, and each conductor plate is used in power-supply wiring or ground wiring.
申请公布号 JP4474431(B2) 申请公布日期 2010.06.02
申请号 JP20070078810 申请日期 2007.03.26
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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