| 摘要 |
An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages. The source and drain terminals of a first one of the pair of differential input transistors are electrically connected to corresponding source and drain terminals of a first one of the pair of differential offset compensation transistors and the source and drain terminals of a second one of the pair of differential input transistors are electrically connected to corresponding source and drain terminals of a second one of the pair of differential offset compensation transistors.
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