发明名称 Memory device, memory controller and memory system
摘要 The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
申请公布号 US7729200(B2) 申请公布日期 2010.06.01
申请号 US20070000840 申请日期 2007.12.18
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 IKEDA HITOSHI;SATO TAKAHIKO;KANDA TATSUYA;UCHIDA TOSHIYA;KOBAYASHI HIROYUKI;SHIRAKAWA SATORU;MIYAMOTO TETSUO;YAMAMOTO YOSHINOBU;OTSUKA TATSUSHI;TAKAHASHI HIDENAGA;KURITA MASANORI;KAMATA SHINNOSUKE;SATO AYAKO
分类号 G11C7/10 主分类号 G11C7/10
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