发明名称 |
Systems and methods for issuing address and data signals to a memory array |
摘要 |
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address.
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申请公布号 |
US7729182(B2) |
申请公布日期 |
2010.06.01 |
申请号 |
US20080203533 |
申请日期 |
2008.09.03 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
BRINGIVIJAYARAGHAVAN VENKATRAGHAVAN;BROWN JASON |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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