发明名称 |
Pipelined instruction processor with data bypassing and disabling circuit |
摘要 |
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.
|
申请公布号 |
US7730284(B2) |
申请公布日期 |
2010.06.01 |
申请号 |
US20050549368 |
申请日期 |
2005.09.14 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
SRINIVASAN BALAKRISHNAN;SETHURAMAN RAMANATHAN;ALBA PINTO CARLOS ANTONIO |
分类号 |
G06F9/30;G06F9/38;G06F9/45 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|