| 摘要 |
Provided is a flash memory device including a plurality of page buffer high voltage transistors. The plurality of high voltage transistors are operatively associated with a page buffer circuit, wherein each high voltage transistor includes; a gate pattern separating a first pattern from a second pattern. The first and second patterns extend in parallel and serve as respective source/drain regions, and the first pattern is floated and the second pattern receives an erase voltage during an erase operation. A first set of high voltage transistors is series connected in a columnar arrangement, such that column adjacent high voltage transistors are laid out with alternating source/drain symmetry in the columnar direction.
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