发明名称 SUB-CIRCUIT PATTERN RECOGNITION IN INTEGRATED CIRCUIT DESIGN
摘要 A method and system for sub-circuit pattern recognition in integrated circuit design is disclosed. In one embodiment, a method for recognizing a pattern circuit in a target circuit, includes encoding the pattern circuit and the target circuit by processing a first netlist of the pattern circuit and a second netlist of the target circuit, generating a cross-linked data structure based on attributes and connectivity information of at least two devices and at least one net from the first netlist, and identifying an instance of the pattern circuit in the target circuit based on an associative mapping between the pattern circuit and a sub-circuit of the target circuit using a device integer array and a net integer array. Each of the first netlist and the second netlist is based on the at least two devices and the at least one net connecting the at least two devices.
申请公布号 US2010131908(A1) 申请公布日期 2010.05.27
申请号 US20080323483 申请日期 2008.11.26
申请人 KRISHNAN SANDEEP SHYLAJA 发明人 KRISHNAN SANDEEP SHYLAJA
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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