发明名称 VARIABLE DELAY CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a variable delay circuit allowing a predetermined delay time to be set. Ž<P>SOLUTION: The variable delay circuit is equipped with a first delay circuit 6, a second delay circuit 7, a detection circuit 8, and a selection circuit 9. The first delay circuit 6 is configured by cascading a plurality of first delay stages 6a and an input signal is received by an initial stage of them. The second delay circuit 7 is configured by cascading a plurality of second delay stages 7a as many as the first delay stages 6a, and a first timing signal is received by the initial stage. The detection circuit 8 receives a second timing signal, and a delay timing signal having a transition edge adjacent to a transition edge of the second timing signal is determined among delay timing signals output from each of the second delay stages 7a. The selection circuit 9 selects the delay signal output from the first delay stage corresponding to the second delay stage which outputs the delay timing signal determined by the detection circuit 8. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010118143(A) 申请公布日期 2010.05.27
申请号 JP20100032109 申请日期 2010.02.17
申请人 FUJITSU MICROELECTRONICS LTD 发明人 TOMITA HIROYOSHI
分类号 G11C11/4076;H03K5/135 主分类号 G11C11/4076
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