发明名称 IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD
摘要 A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.
申请公布号 US2010131259(A1) 申请公布日期 2010.05.27
申请号 US20080324170 申请日期 2008.11.26
申请人 JOSHI RAJIV V;KANJ ROUWAIDA 发明人 JOSHI RAJIV V.;KANJ ROUWAIDA
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址