MOUNTED CACHE MEMORY IN A MULTI-CORE PROCESSOR (MCP)

摘要

Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system. It should be understood in advance the teachings herein are typically applied to a Multi-Core Processor (MCP), although this need not be the case