| 摘要 |
PURPOSE: An error judging circuit and a shared memory system are provided to improve the usage efficiency of a main memory region without increasing a cost. CONSTITUTION: A shared memory system has a structure in which a plurality of nodes(1) are connected by a well-known connection means(2). The node includes a processor(11) such as a CPU(Central Processing Unit), a DC(Directory Controller)(12), a main storage memory(13), and a cache memory(14). Since a ccNUMA system is employed, in addition to data, directory information for keeping the coherency of the data that is stored in the cache memory is stored in the main storage memory. An encoding circuit includes a first EOR circuit tree for generating a check bit of a correction code by using a polynomial remainder calculation of C(X)=X<2>I(X)modP(x) with respect to a polynomial expression I(x) of an original code of a target which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2<m>) (m is a natural number not less than 8) in SmEC-DmED using (k, k-3) Reed-Solomon code (k is a natural number not more than 2<m>) when P(x) is a primitive polynomial of m-order in a Galois field GF, a primitive element in the Galois extension field GF (2<m>) is [alpha], and a root of P(x)=0 is [alpha]<i> (i=0, ..., m-1). On the other hand, a decoding circuit includes a second EOR circuit tree for generating syndromes S0, S1, S2 from Sn=Y([alpha]<n>) (n=0, 1, 2) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is a target to be detected and has the possibility that an error is mixed is Y(x), and an error detection circuit unit for detecting that there is a one block error, a two block error, or no error based on whether or not S1<2>=S0S2 is satisfied and for detecting a position p of a block error from S0[alpha]<p>=S1 in the Galois extension field GF(2<m>). As described below, an error judging circuit includes the first EOR circuit tree, the second EOR circuit tree, and the error detection circuit unit.
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