| 摘要 |
A computer-implemented method of improving timing of a circuit design for a programmable logic device can include identifying a timing critical wire of the circuit design and determining a fanout free cone coupled to a plurality of leaf nodes, wherein the critical wire links a critical leaf node of the plurality of leaf nodes with the fanout free cone. At least one leaf node set can be selected, wherein the leaf node set includes a plurality of symmetric leaf nodes including the critical leaf node and at least one non-critical leaf node. At least two leaf nodes of a leaf node set can be swapped in the circuit design. The circuit design can be output.
|
