发明名称 FPGA configuration bitstream protection using multiple keys
摘要 Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
申请公布号 US7725738(B1) 申请公布日期 2010.05.25
申请号 US20050042477 申请日期 2005.01.25
申请人 ALTERA CORPORATION 发明人 LANGHAMMER MARTIN;JOYCE JUJU;STREICHER KEONE;JEFFERSON DAVID;REDDY SRINIVAS;PRASAD NITIN
分类号 G06F12/14 主分类号 G06F12/14
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