发明名称 Solder bump confinement system for an integrated circuit package
摘要 A solder bump confinement system is provided including providing a substrate, patterning a contact material on the substrate, depositing an inner passivation layer over the contact material and the substrate, forming an under bump material defining layer over the contact material by sputtering, and forming a system interconnect over the contact material and on the under bump material defining layer.
申请公布号 US7723225(B2) 申请公布日期 2010.05.25
申请号 US20070671900 申请日期 2007.02.06
申请人 STATS CHIPPAC LTD. 发明人 LIN YAOJIAN;MARIMUTHU PANDI CHELVAM;PENDSE RAJENDRA D.
分类号 H01L21/44 主分类号 H01L21/44
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