| 摘要 |
A display unit is constituted by a passive matrix of independently controllable pixels characterized by an active area of n rows and m columns of discrete pixels and a pixel border. The pixel border has a predetermined width, in one embodiment two pixels. The border pixel color state is controlled herein by the frame buffer memory. The pixel border color state is controlled to correspond to information contained in a frame buffer memory locus. This locus may be, in various embodiments herein, a single pixel, a row of pixels, or a number of rows of pixels of frame buffer memory. Each row of pixels may be equal to m and/or n. In one embodiment, the frame buffer controls the border pixels directly via a liquid crystal display controller and drivers, without a timing generation mechanism, such as a timing ASIC.
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