发明名称 VERTICAL BIPOLAR TRANSISTOR, AND METHOD OF MANUFACTURING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a vertical bipolar transistor having been subjected to salicide processing through which a base-side depletion layer sufficiently spreads by forming a salicide offset region to prevent problems such as a leakage current and a decrease in junction breakdown voltage. SOLUTION: The vertical bipolar transistor includes a collector region 2 of a first conductivity type (N type) formed on a semiconductor substrate 1, a base region 5 of a second conductivity type (P type) formed in the collector region 2, an emitter region 6 of the first conductivity type formed in the base region 5, a field oxide film 4 formed at a surface part of the collector region 2 while enclosing the base region 5, and a salicide layer 14 formed on the base region 5. A surface of the base region 5 is provided with a salicide region where a salicide layer 14 is formed and a salicide offset region 15 where the salicide layer is not formed between an end of the field oxide film 4 and an end of the salicide region. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010114292(A) 申请公布日期 2010.05.20
申请号 JP20080286277 申请日期 2008.11.07
申请人 SEIKO NPC CORP 发明人 ANZAI KIYOSHI
分类号 H01L21/331;H01L21/28;H01L29/417;H01L29/732 主分类号 H01L21/331
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