| 摘要 |
A computer system (10) includes a system memory (14), a plurality of processor cores (15A, 15B), and an input/output (I/O) hub (13A) that may communicate with each of the processor cores. In response to detecting an occurrence of an internal system management interrupt (SMI), each of the processor cores may save to a system management mode (SMM) save state in the system memory, information corresponding to a source of the internal SMI. In response to detecting the internal SMI, each processor core may further initiate an I/O cycle to a predetermined port address within the I/O hub. The I/O hub may broadcast an SMI message to each of the processor cores in response to receiving the I/O cycle. Each of the processor cores may further save to the SMM save state in the system memory, respective internal SMI source information in response to receiving the broadcast SMI message.
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