DIGITAL SIGNAL PROCESSING APPARATUS

摘要

PROBLEM TO BE SOLVED: To reduce data capacity of an address memory which stores an address data used for accessing a delay memory.

SOLUTION: A DSP (digital signal processor) 6 with the delay memory 10 includes: the address memory 13 for storing the address data of the number less than the number of all steps accessible to the delay memory 10; a microprogram memory 11 which stores a micro program composed of the predetermined number of steps of microcodes; a step counter 12 for generating a first count value for reading microcodes for each step; an access counter 14 for generating a second count value for each access instruction to the delay memory 10; and a delay memory access section 15. The address data are read from the address memory 13 by using the second count value for each access instruction. The delay memory access section 15 accesses the delay memory 10 by using the read address data.

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