发明名称 DATA CONVERSION APPARATUS
摘要 PROBLEM TO BE SOLVED: To reduce the capacity of an RAM required for interpolation operation sharply by using a consecutive address for accessing an LUT while enabling high speed processing. SOLUTION: The data conversion apparatus includes a lookup table 30 which stores output data at the addresses of 125 lattice point coordinates which is expressed by four combinations of 2 significant bits of input data RGB each consisting of 8 bits and one combination for interpolation, an address generating unit 20 which generates a plurality of addresses for reading out the output data from the lookup table 30 according to the input data RGB, and an interpolation operation unit 40 which generates converted data based on the plurality of output data read out from a plurality of addresses generated at the address generating unit 20 and the input data RGB. The lookup table 30 divides the 125 lattice point coordinates into 8 sets according to the fact whether the value expressed by 2 significant bits of input data RGB is odd or even, and 8 RAMs are provided in correspondence with the 8 sets of lattice point coordinates in order to store the output data at the continuous addresses of each RAM. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010114542(A) 申请公布日期 2010.05.20
申请号 JP20080283851 申请日期 2008.11.05
申请人 KAWASAKI MICROELECTRONICS INC 发明人 IZUMI TAKETO
分类号 H04N1/46;G06T1/00;H04N1/60 主分类号 H04N1/46
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