发明名称 VIDEO RATE CONTROL PROCESSOR FOR A VIDEO ENCODING PROCESS
摘要 A system for executing video encoding operations. The system includes a video encoder for encoding an incoming video stream into a plurality of macro blocks. A motion estimation engine is coupled to the video encoder for controlling the encoding of the macro blocks. A video rate control processor is coupled to the video encoder and coupled to the motion estimation engine. The video rate control processor receives a plurality of parameters from the video encoder that indicate an encoding complexity for a macro block and a video frame of the video stream and, upon receiving an indication from the motion estimation engine, computes a quantization parameter for the macro block. The quantization parameter is dynamically adjusted for the video stream to achieve a target bit rate.
申请公布号 US2010124279(A1) 申请公布日期 2010.05.20
申请号 US20080274237 申请日期 2008.11.19
申请人 NVIDIA CORPORATION 发明人 REDDY HARIKRISHNA MADADI;CHOUDHURY HIMADRI;PARHY MANINDRA;CHENG LIANG
分类号 H04N7/26 主分类号 H04N7/26
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