| 摘要 |
A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.
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