| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve system performance by reducing an operation cost of inter-processor interruption. <P>SOLUTION: The sequence of the inter-processor interruption of a sender side processor side includes the followings. The memory writing of an inter-processor interruption requests to a linear address X is carried out (305). A sender side processor determines whether a value is changed or not by polling a specific memory location, and waits a positive response for receiving the inter-processor interruption from the receiver side processor (310). If the memory location has changed its value, a normal operation is resumed (315). <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
