| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To suppress the circuit scale of a delay device. <P>SOLUTION: A DLL circuit 120 generates a first control signal CTR1 for controlling a delay element 122 so that a reference clock inputted to a delay element 122 can be delayed one cycle by a delay element 122. A delay element 140 has the same configurations as that of the delay element 122, and is configured to delay a strobe signal S1 from the outside according to an amounts of delay corresponding to a second control signal CTR2. A strobe delay control circuit 130 generates a second control signal CTR2 to be output to the delay element 140 from the first control signal CTR1 and the expected value of the amount of delay by the delay element 140. A clock supply circuit 110 provides a reference clock having frequency higher than the frequency of the strobe signal S1 inputted to the delay element 140 to a DLL circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
