| 摘要 |
To provide a plurality of DRAM cells, a plurality of sense amplifiers connected to corresponding bit line pairs, a first column switch and a second column switch assigned to each of the sense amplifiers, data lines connected via the column switches to the sense amplifiers, a first port PORT1 and a second port PORT2 that can input/output write data and read data, and an input/output circuit that connects the PORT1 and the PORT2 to the data lines. Thus, a pseudo dual-port memory can be configured by using an ordinary DRAM array.
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