Read circuit for semiconductor memory device and semiconductor memory device

摘要

Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers (A1-A4) of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal (20), if a number of byte selectors (B0-B3) which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers (A1-A4) are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale. The four sense amplifiers (A1-A4) are thus shared by subsequent sets of data bits from the byte selectors (B0-B3) and the first set of data bits from the sense amplifiers (A1-A4) is latched in data latches (L1-L4) so that the sense amplifiers (A1-A4) can sense a second set of data bits before output of a selected one of the first data bits from one of the latches (L1-L4).