| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which obviates measures to cope with non-synchronism or skew matching when transferring data during reception or transmission between a high-speed operating block and a low-speed operating block. <P>SOLUTION: A high-speed operating block 1 comprises: a shift register 12 for performing serial/parallel data conversion based on a load enable signal ld-en; a clock generation block 17 for generating a clock CLK-B having a cycle of an integer multiple of a clock CLK-A in accordance with a count value of the clock CLK-A; and a sampling circuit 15 which generates the load enable signal ld-en having the same cycle as the clock CLK-B in accordance with the count value of the clock CLK-A and supplies it to the shift register 12. <P>COPYRIGHT: (C)2008,JPO&INPIT |
