发明名称
摘要 <P>PROBLEM TO BE SOLVED: To obtain an output signal having a waveform and a phase matched between working/reserve modulators, even if a clock inputted into the modulators is 10 MHz. <P>SOLUTION: A clock converter 20 comprises a 1/315 divider 21 for dividing a 10 MHz clock into 2/63 MHz, a VCO 24 for oscillating a 512/63 MHz clock and controlling its oscillation frequency according to a voltage signal, a 1/256 divider 25 for dividing the 512/63 MHz clock from the VCO 24 into 1/256, a phase comparator 23 for comparing the output clock of the dividers 21 and 25 and for outputting a pulse signal used as the voltage signal according to the phase difference, and a waveform shaper 22 for receiving a frame synchronization signal indicative of the period of a multiplex frame for digital broadcasting and the 10 MHz clock as input and shaping a pulse waveform of the frame synchronization signal to synchronize with the 10 MHz clock, and outputting the shaped signal as a reset signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP4465658(B2) 申请公布日期 2010.05.19
申请号 JP20040310119 申请日期 2004.10.25
申请人 发明人
分类号 H04L7/033;H03L7/00;H04B1/04;H04L7/04;H04N5/38 主分类号 H04L7/033
代理机构 代理人
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