| 摘要 |
Divider circuitry for a phase-locked loop frequency synthesizer, the divider circuitry comprising
a main divider configured to divide an input signal received from a feedback path of the phase-locked loop frequency synthesizer by a division ratio selected from a pair of dual modulus division ratios in accordance with a dual modulus selection signal; and
an auxiliary divider comprising a shift register clocked by an output signal of the main divider, the shift register comprising a parallel input configured to receive parallel input data in the form of a fraction selection signal at the start of a cycle, and a serial output connected to a control input of the main divider, the auxiliary divider being configured to produce serial output data, each bit of which serves as a said dual modulus selection signal to cause the main divider to operate using one or the other of the pair of dual modulus main division ratios;
the auxiliary divider being configured to produce a pulse once per cycle of the shift register and to output the pulse to a phase detector of the phase-locked loop frequency synthesizer.
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