| 摘要 |
PURPOSE: A DLL(delay locked loop) circuit is proved to shorten a locking time by controlling phase of the output clock at high speed when the phase difference of a reference clock and a feedback clock is over a set range. CONSTITUTION: A first feedback loop(20) performs delay locking of a first reference clock and generates the delay clock of a multi-phase. A clock selector(30) outputs one of delay clocks of a multi-phase to a second reference clock in response to a phase sense signal. A second feedback loop(40) receives the first reference clock and performs delay locking of the second reference clock through feedback of one clock of delay clocks of a multi-phase. |
