发明名称 Receiver ADC clock delay base on echo signals
摘要 A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.
申请公布号 US7720015(B2) 申请公布日期 2010.05.18
申请号 US20050205615 申请日期 2005.08.17
申请人 TERANETICS, INC. 发明人 GUPTA SANDEEP KUMAR;TELLADO JOSE
分类号 H04B3/20 主分类号 H04B3/20
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