发明名称 Method and apparatus of estimating circuit delay
摘要 Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert signal transition features into an effective fanout to provide estimates of gate delay dependencies on input slope and gate logic topology.
申请公布号 US7721236(B2) 申请公布日期 2010.05.18
申请号 US20060532878 申请日期 2006.09.18
申请人 QUALCOMM INCORPORATED 发明人 HWANG MYEONG-EUN;JUNG SEONG-OOK
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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