发明名称 Method, system, and computer program product for timing closure in electronic designs
摘要 Disclosed is a method, system, and computer program product for timing closure with concurrent models for fabrication, metrology, lithography, and/or imaging processing analyses for electronic designs. Some embodiments of the present invention disclose a method for timing closure with concurrent process model analysis which comprises the act of generating a design for the one or more interconnect levels; analyzing the effects of the concurrent models to predict feature dimension variations based upon the concurrent models; modifying the design files to reflect the variations; determining one or more parameters based upon the concurrent models; and determining the impact of concurrent models upon the electrical and timing performance. Some embodiments disclose a computerized system for implementing the method(s) disclosed herein. Some embodiments also disclosed a computer program product comprising executable code for the method(s) disclosed herein.
申请公布号 US7721237(B2) 申请公布日期 2010.05.18
申请号 US20070866376 申请日期 2007.10.02
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 SCHEFFER LOUIS K.;WHITE DAVID
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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