发明名称 Packet-parallel high performance cryptography systems and methods
摘要 A cryptographic system (500) includes cryptographic sub-units (510) and associated input buffers (520) connected to a scheduler (530) and a reassembler (540). The scheduler (530) receives packets, where each of the packets includes one or more data blocks, and assigns each of the packets to one of the sub-units (510). The input buffers (520) temporarily store the packets from the scheduler (530). Each of the sub-units (510) performs a cryptographic operation on the data blocks from the associated input buffer (520) to form transformed blocks. The reassembler (540) receives the transformed blocks from the sub-units (510), reassembles the packets from the transformed blocks, and outputs the reassembled packets in a same order in which the packets were received by the scheduler (530).
申请公布号 US7721086(B2) 申请公布日期 2010.05.18
申请号 US20080347170 申请日期 2008.12.31
申请人 VERIZON CORPORATE SERVICES GROUP INC. & BBN TECHNOLOGIES CORP. 发明人 MILLIKEN WALTER CLARK
分类号 G06F7/76;G06F11/30 主分类号 G06F7/76
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