发明名称 |
CD gate bias reduction and differential N+ poly doping for CMOS circuits |
摘要 |
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.
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申请公布号 |
US7718482(B2) |
申请公布日期 |
2010.05.18 |
申请号 |
US20070928872 |
申请日期 |
2007.10.30 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
EKBOTE SHASHANK;OBRADOVIC BORNA;BALDWIN GREG C. |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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