| 摘要 |
659,576. Non-linear circuits ; pulse code modulation circuits. STANDARD TELEPHONES & CABLES, Ltd. Dec. 24, 1948, No. 33225. Convention date, Feb. 26. [Classes 40 (v) and 40 (vi)] A signal is applied to N differently biassed rectifiers feeding n voltage dividers (where n#N), the output voltages from the dividers being combined to give a desired characteristic which may be logarithmic. A signal, which may comprise amplitude-modulated pulses, is applied from source 1, Fig. 4, to a series of rectifiers 3, individually biassed from potential divider 5. The output from load resistor 4 is applied over the dividing network 11, 18 to the primary of transformer 20. In a similar manner, the outputs from the other rectifiers are applied through suitable resistors 13, 15 and 17 to the primary of the transformer. As certain components are required in a negative sense they are fed over networks.12, 14, 16 and 19 to the primary of transformer 20 to oppose the voltages set up by the. first series. For pulse code modulation using a three-element code, combining circuits A, B and C are employed having input/output characteristics as shown in Fig. 3. Delay devices 22, 23 are employed in order that the final output pulses may be suitably spaced in time. In a modification, Fig. 5, the outputs from the dividers 11 ... 19 are fed to equi-gain amplifiers 23, 24 to produce an out-of-phase or in-phase signal. These are subtracted in the grid circuit of valve 28, a capacitor 29 in the anode circuit being charged accordingly. When capacitor 29 has been charged negatively to cut off valve 31, a gating pulse applied to valve 32 causes the common anode potential to rise and a positive pulse to pass to the output. Gating pulses are applied in sequence over leads 34, 35, 36 to produce the three successive output pulses. The circuits may be given more sharply defined characteristics, Fig. 6 (not shown), by using a larger number of rectifiers. In a further modification, Fig. 8 (not shown), positive and negative pulses are applied to a series of rectifiers biassed positively and negatively, the outputs being summed over a simple potential divider. In order to avoid incorrect coding at certain input levels, further rectifiers may be connected between the output of each rectifier and the next more positive tap on divider 5, Fig. 9 (not shown). Since zero output may occur over narrow ranges, a circuit giving a small output for no input may be applied in a feed-back connection between the output of the combining circuits and the signal input, Fig. 7 (not shown). |
