发明名称 Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system
摘要 A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.
申请公布号 US7719921(B2) 申请公布日期 2010.05.18
申请号 US20080170730 申请日期 2008.07.10
申请人 ELPIDA MEMORY, INC. 发明人 KUROKI KOJI;TAKAI YASUHIRO
分类号 G11C11/00 主分类号 G11C11/00
代理机构 代理人
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