发明名称 |
PROGRAMMIERBARE LOGISCHE VORRICHTUNG MIT VEREINHEITLICHTER ZELLSTRUKTUR UND MIT SIGNALVERBINDUNGSSCHWELLEN |
摘要 |
A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball. |
申请公布号 |
AT466409(T) |
申请公布日期 |
2010.05.15 |
申请号 |
AT20060000671T |
申请日期 |
2000.07.14 |
申请人 |
ALTERA CORPORATION |
发明人 |
SHUMARAYEV, SERGEY;HUANG, WEI-JEN;PATEL, RAKESH |
分类号 |
H01L27/04;H03K19/177;G06F7/38;H01L21/82;H01L21/822;H01L25/00;H01L27/02;H01L27/118;H05K3/40;H05K7/02 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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