| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an A/D converter achieving a high SNR without increasing an occupancy area or current consumption. Ž<P>SOLUTION: The A/D converter includes: one sample hold part 1 for sampling input analog signals at predetermined timing, holding m (m≥2) same analog values, and time-sequentially and continuously outputting the m same analog values held; an A/D conversion part 2 for time-sequentially converting the m same analog values time-sequentially and continuously input from the sample hold part 1 to m digital signals; a data arrangement adjustment circuit 3 for adjusting the timing and parallelizing the m digital signals time-sequentially and continuously input from the A/D conversion part 2; and an averaging circuit 4 for outputting the average value of the m digital signals input in parallel from the data arrangement adjustment circuit 3 as a final A/D conversion result. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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