Scalable Decoder Architecture for Low Density Parity Check Codes

摘要

A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.