| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase interpolation circuit for generating a clock signal of a desired phase without performing signal superimposition in a linear area. <P>SOLUTION: The phase interpolation circuit includes: a pulse string generation circuit which generates a pulse string including a first pulse of the same phase as that of the pulse of a reference timing signal having a fixed frequency and phase and a second pulse of a phase deviated from that of the pulse of the reference timing signal; and a pulse phase averaging circuit which generates an output pulse signal having a pulse at a fixed phase position according to the weighted average of the phase of the first pulse and the phase of a second pulse, according to the pulse string. The weight of the weighted average is a weight according to the ratio of the number of the first pulses to the number of the second pulses included in the pulse string within a predetermined period. <P>COPYRIGHT: (C)2010,JPO&INPIT |
