| 摘要 |
A DLL circuit includes a delay unit configured to generate a DLL clock signal by delaying a reference clock signal while adjusting a delay amount in response of a level of a control voltage. An initial operation control unit is configured to control an initial level of the control voltage and generate a detection enable signal. A delay control unit is configured to generate the control voltage by comparing a phase of the reference clock signal and a phase of the DLL clock signal in response to the detection enable signal.
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