发明名称 SCAN FLIP-FLOP WITH INTERNAL LATENCY FOR SCAN INPUT
摘要 A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.
申请公布号 KR20100047191(A) 申请公布日期 2010.05.07
申请号 KR20097026191 申请日期 2008.05.07
申请人 ATI TECHNOLOGIES ULC 发明人 AHMADI RUBIL
分类号 H03K3/356;H03K5/14 主分类号 H03K3/356
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