发明名称 SYSTEMS AND METHODS FOR IMPROVING DIGITAL SYSTEM SIMULATION SPEED BY CLOCK PHASE GATING
摘要 An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.
申请公布号 US2010114551(A1) 申请公布日期 2010.05.06
申请号 US20080265661 申请日期 2008.11.05
申请人 QUALCOMM INCORPORATED 发明人 KAZI TAUSEEF;YU HAOBO;CAI LUKAI;SRIDHARAN MAHESH;CHAIYAKUL VIRAPHOL
分类号 G06F17/50 主分类号 G06F17/50
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