| 摘要 |
A digital electronic device is provided which comprises a digital clock deviation detecting means and a digital clock correcting means. The clock deviation detecting means is used to detect a deviation of a first clock signal of the electronic device and/or the duty cycle of the first clock signal. The clock correcting means is used to correct the first clock signal and/or the duty cycle of the first clock signal if the clock deviation detecting means has detected a deviation of the first clock signal and/or the duty cycle of the first clock signal. The clock correcting means comprises at least a first and second compensation path (P1, P2) for compensating deviations in the first clock signal and/or the duty cycle thereof, when the first clock signal passes through the first or second path. The first path (P1) does not induce a compensation and is selected if the clock deviation detecting means has not detected a deviation in the first clock signal. The second path (P2) includes a first compensation and is selected if the clock deviation detecting means has detected a deviation of the first clock signal.
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