Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.
申请公布号
WO2010051211(A2)
申请公布日期
2010.05.06
申请号
WO2009US61626
申请日期
2009.10.22
申请人
FAIRCHILD SEMICONDUCTOR CORPORATION;JEREZA, ARMAND, VINCENT, C.