发明名称 CLOCK DIVISION CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD
摘要 <p>A clock division circuit (11) masks (S - N) clock pulses among S clock pulses of an input clock signal according to a division ratio defined by an N/S and generates an output clock signal obtained by N/S-dividing the input clock signal.  The clock division circuit (11) includes a mask control circuit (40) and a mask circuit (50).  The mask control circuit (40) generates a mask signal by allocating a non-mask timing with a higher priority, to clock pulses at the timings where no clock pulse exists in the clock signal used by a circuit Ai other than a target circuit Bi using the output clock signal among the S clocks of the input clock signal.  The mask circuit (50) masks the clock pulse of the input clock signal in accordance with the mask signal generated by the mask control circuit so as to generate an output clock signal.</p>
申请公布号 WO2010050098(A1) 申请公布日期 2010.05.06
申请号 WO2009JP03633 申请日期 2009.07.30
申请人 NEC CORPORATION;SHIBAYAMA, ATSUFUMI 发明人 SHIBAYAMA, ATSUFUMI
分类号 H03K23/64;G06F1/04;G06F1/08;G06F1/10;H03K5/15 主分类号 H03K23/64
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