| 发明名称 |
TEST ARRANGEMENT, POGO-PIN AND METHOD FOR TESTING A DEVICE UNDER TEST |
| 摘要 |
<p>A test arrangement (400) comprises an interface (401) for a device under test (404), the interface (401) comprising an impedance matching circuit (402) comprising a resistance (R) and an inductance (L) connected in parallel.</p> |
| 申请公布号 |
WO2010048971(A1) |
申请公布日期 |
2010.05.06 |
| 申请号 |
WO2008EP09178 |
申请日期 |
2008.10.30 |
| 申请人 |
VERIGY (SINGAPORE) PTE., LTD.;LAQUAI, BERND |
发明人 |
LAQUAI, BERND |
| 分类号 |
G01R1/067;H01R13/24;H03H7/38;H05K7/10 |
主分类号 |
G01R1/067 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
