发明名称 |
OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMING INFORMATION |
摘要 |
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
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申请公布号 |
US2010115477(A1) |
申请公布日期 |
2010.05.06 |
申请号 |
US20090624395 |
申请日期 |
2009.11.23 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
ALBRECHT CHRISTOPH;CHONG PHILIP;KUEHLMANN ANDREAS;SENTOVICH ELLEN;PASSERONE ROBERTO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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