| 摘要 |
PROBLEM TO BE SOLVED: To reduce output of a WAIT signal to maintain data consistency to effectively process subsequent memory access when there is no subsequent memory access at the time of miss hit in a cache memory having a multi-stage pipeline structure. SOLUTION: The cache memory performs update processing of a tag memory 11 and a data memory 10 and decides whether or not there is a subsequent memory access when a hit decision unit 12 decides that an input address is a miss hit. Upon decision that there is a subsequent memory access, a controller outputs a WAIT signal to generate a pipeline stall for the pipeline processing of the processor to the processor 2, while the controller does not output a WAIT signal upon decision that there is no subsequent memory access. COPYRIGHT: (C)2010,JPO&INPIT |
